User equipment such as mobile telephones are known. These devices are arranged to be able to transmit signals and receive signals. There are several different standards which are being used worldwide at the present time. By way of example only, these standards include GSM (global system for mobile communication) 900, GSM 1800, WCDMA (wideband code division multiple access). One or more of these different systems may be used in the same country. Alternatively, different systems may be used in different countries. Additionally different standards may exist for different types of communication such as voice and data.
Multimode user equipment is known. These types of devices are capable of dealing with more than one of these standards. To deal with more than one of these standards, the transmitters of these phones have so far been designed in such a way such that they have a relatively high power consumption. Furthermore, the size of the transmitter is relatively large as is the cost of such a transmitter. This is a result of the requirement to deal with more than one standard or mode. The transmitter may need to be able to have a large operational bandwidth and/or linearity.
Reference is made to T. Sowlati, D. Rozenblit, R. Pullela, M. Damgaard, E. McCarthy, D. Koh, D. Ripley, F. Balteanu, I. Gheorghe, “Quad-band GSM/GPRS/EDGE polar loop transmitter” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004. This document describes the polar loop transmitter discussed in relation to FIG. 1 which is arranged to deal with a wide range of bandwidths. This is a polar loop transmitter. The known transmitter 2 comprises a first loop 4 for controlling the phase and a second loop 6 for controlling the amplitude of the transmitted signal.
An antenna 8 is provided. The transmitter 2 is connected to the antenna 8 via a switch 10. This switch allows the transmitter or a receiver (not shown) to be connected to the antenna. The phase loop 4 has an output which is connected to the input of a power amplifier 12. The power amplifier 12 has a control input Vcntrl 14 which is an output of the amplitude loop 6. The controls the amplification provided by the amplifier.
The phase loop 4 comprises an ultra high frequency UHF voltage controlled oscillator 20. The output of this oscillator 20 is connected to a first divider 22 which divides the frequency by M. The output of the first divider 22 is connected to a second divider 24 which divides the output of the first divider 24 by N. This provides an intermediate frequency reference IFref. The output of the second divider 24 is input to a phase frequency detector 26 the output of which is connected to a charge pump 28. The charge pump 28 has an output connected to a first low pass filter 30. The output of the first low pass filter 30 is connected to a radio frequency voltage controlled oscillator 32, the output of which is connected to a first amplifier 34.
The output of the first amplifier 34 represents the output of the phase loop 4 and is input to the power amplifier 12. It should be appreciated that the signal which is output by the first amplifier will have the required phase and will be at the required radio frequency.
The phase loop 4 also has an output 40 from between the first divider 22 and the second divider 24. The output 40 of the phase loop is input to a mixer 42 of the amplitude loop 6. Before being output of the phase loop, the output passes through a buffer 38.
The phase loop also has a first bandpass filter 44, the output of which is connected to a second amplifier 46. The input to the first bandpass filter 44 is a feedback path from the output of the power amplifier, via part of the amplitude loop as will be described in more detail hereinafter. The second amplifier 46 has an output connected to an IQ modulator 48. The IQ modulator has a base band I and Q input. The output of the IQ modulator is effectively at the intermediate frequency but is a modulated signal. The output of the IQ modulator 48 is input to a limiter 54, the output of which is connected to a second input of the phase frequency detector 26. The phase frequency detector will compare the phase of the modulated version of the intermediate frequency with the reference version of the intermediate frequency.
The output provided by the phase frequency detector 26 effectively has an output which instructs subsequent circuitry on how to adjust in order to lock onto the phase. The output of the phase frequency detector 26 is fed to the filter 30 which integrates the signal to smooth it. This smoothed signal is fed to the voltage-controlled oscillator. The VCO provides an output signal with a RF frequency that is proportional to the level of the input voltage, which is then fed back to the PFD 26.
The output of the IQ modulator 48 is additionally input to a second bandpass filter 50, the output of which is connected to an amplifier 52. The output of that amplifier 52 is input to a first detector 54 of the amplitude loop.
The amplitude loop 6 will now be described. A coupler 70 is provided between the power amplifier 12 and the switch 10. A small proportion of the output signal is input to a mixer 42. The mixer 42 mixes the output received from the coupler with the output 40 received from the phase loop 4 to provide an intermediate frequency signal. The output of the mixer 42 is input to an intermediate frequency voltage gain amplifier VGA 62. The output of this amplifier 62 is connected to a limiter 64, the output of which is connected to the first band pass filter 44 of the amplitude loop.
The output of the intermediate frequency voltage gain controlled amplifier 62 is also input to a second detector 60. The output of the first and second detectors 60 and 68 are input to a subtractor 70 which subtracts one value from the other to define an error value. The error value is input to a baseband VGA 72. The output of the baseband VGA 72 is input to a second low pass filter 74. The output of the second low pass filter 74 is input to a third amplifier 76, the output of which provides the voltage control signal 14 for the power amplifier 12. In other words the error signal will define the control signal applied to the power amplifier and hence the required amplitude of the output signal.
Effectively, the phase loop works by comparing an intermediate frequency reference signal generated by the UHF VCO and the first and second dividers with a modulated intermediate frequency signal. The modulated intermediate frequency signal is generated by the IQ modulator. The modulated signal is limited by the limiter 54 to keep the signal within required bounds. The phase frequency detector uses these inputs to provide an output with the required phase information. This signal is effectively processed and output at a radio frequency level to the power amplifier.
The amplitude loop 6 generates an error value from comparing a feedback signal with the modulated intermediate frequency signal. The feedback signal is taken by the coupler, passes through the mixer and VGA 62 to provide the feedback signal at the intermediate frequency. The signal with which it is compared is the modulated intermediate frequency signal, which has been filtered by the second band pass filter 50 and amplified by the amplifier 52. This is representative of the signal before it passes through the various components. This error signal is used to generate a control signal which is then used to control the power amplifier to control the amplitude of the transmitted signal. The output between the first and second dividers is input to the mixer 42 and is used to down convert the signal received from the coupler to an intermediate frequency.
Thus the arrangement of FIG. 1 uses two loops in controlling the transmitted signal, one for phase and one for amplitude. This arrangement produces a good transmitter, but the arrangement requires a large number of components including a power amplifier, gain controlled amplifiers (VGA), mixers, and a number of voltage controlled oscillators. This means that the transmitter has a relative large power consumption and transmitter size/cost. These components are provided to deal with the requirements of a multimode transmitter environment.
Reference is made to U.S. application Ser. No. 11/895,727 which discloses an antenna which has a PM branch output and a AM branch output which are combined in an antenna.
It is an aim of some embodiments of the invention to address the disadvantages discussed above.